FinFET and method of manufacturing the same

ABSTRACT

A FinFET may include a semiconductor fin having a top surface and a sidewall having different crystal planes. A gate dielectric layer on the top surface and on the sidewall has different thicknesses. A gate electrode is formed on the gate dielectric layer across the top surface and sidewall of the semiconductor fin.

BACKGROUND

1. Field of the Invention

Embodiments relate to a semiconductor device and a method ofmanufacturing the same. More particularly, embodiments relate to a finfield effect transistor (FinFET) and a method of manufacturing the same.

2. Description of the Related Art

A vast amount of research has lately been conducted on nano-CMOS devicetechnology worldwide because the nano-CMOS device technology can beapplied to logic circuits, such as a central processing unit (CPU), andmemories to create high value-added products. With the downscaling ofsystems using silicon semiconductor technology and the increased demandfor low power consumption, devices also need to shrink. Presently, theon-going downscaling in the gate size of devices gives rise to problemswith, especially, a short channel effect (SCE).

Conventional CMOS technology involves forming CMOS devices on a bulksilicon substrate. When a MOS device formed on a bulk silicon substratehas a gate length of 50 nm or less, the characteristics of the MOSdevice are greatly affected by process conditions. A MOS device having achannel length of near 30 nm may still be insufficient for an actualcircuit in terms of performance. Furthermore, an area occupied by asingle actual device does not shrink due to an unreduced space regionformed beside a gate, compared with a conventional device, so that theintegration density of the device is not greatly improved.

Owing to a technical limit in MOS device technology based on a bulksilicon substrate, laborious research into a device formed on asilicon-on-insulator (SOI) substrate has progressed in order to formdevices having a channel length of 30 nm or less. There have beenextensive studies on the characteristics of a conventional devicestructure formed on a SOI substrate instead of a bulk silicon substrate.In the device structure formed on the SOI substrate, a parasiticsource/drain resistance greatly increases due to the silicon layerhaving a small thickness, so that separate selective formation of anepitaxial layer in source and drain regions may be needed. Also, since abody of a SOI device is not connected to the substrate, the performanceof the SOI device, for example, a floating body effect and thermalconductivity, may be degraded.

As described above, when a conventional device structure is formed on aSOI substrate, a SOI device is not appreciably shrunk compared with aconventional device based on a bulk silicon substrate. To solve thisproblem, a tri-gate structure or a dual-gate structure has been proposedto reduce a channel length of a CMOS device to 25 nm or less. Thetri-gate structure or dual-gate structure is typically called a finfield effect transistor (FinFET). More specifically, when a channelregion is formed on a protruding pattern, called a fin, having threesurfaces (i.e., a top surface and two sidewalls) on a bulk siliconsubstrate, a tri-gate FinFET is obtained. Also, when a capping layer isformed on the fin of the tri-gate FinFET to cut off a vertical gatefield effect and a channel region is formed on two surfaces (i.e., bothsidewalls) of the fin, a dual-gate FinFET is manufactured.

In the foregoing FinFETs, since a gate electrode is formed on severalsurfaces of a channel region to which current is supplied, the channelregion can be effectively controlled by the gate electrode. Thus, aleakage current flowing between source and drain regions can be greatlyreduced compared with the conventional case, thereby markedly improvinga drain induced barrier lowering (DIBL) effect. Furthermore, the gateelectrode is formed on both sides of the channel region so that thethreshold voltage of a device can be dynamically changed. As a result,the on-off characteristics of the channel region can be notably enhancedcompared with a single gate structure, and the occurrence of an SCE canbe inhibited. Therefore, further advances in FinFET devices andmanufacture are desired.

SUMMARY OF THE INVENTION

Embodiments are therefore directed to a semiconductor device and amethod of manufacturing the same, which overcome one or more of theproblems of the related art.

In an exemplary embodiment, a semiconductor device may include asemiconductor fin having a top surface and a sidewall oriented ondifferent crystal planes, a gate dielectric layer having a first portionon the sidewall of the semiconductor fin and a second portion on the topsurface of the semiconductor fin, the second portion being thicker thanthe first portion, and a gate electrode on the first and second gatedielectric layers.

In an exemplary embodiment, a method may include forming a semiconductorfin having a top surface and a sidewall with different crystal planes,forming a gate dielectric layer including a first portion on thesidewall of the semiconductor fin and a second portion on the topsurface, the second portion being thicker than the first portion, andforming a gate electrode on the first and second portions.

In an exemplary embodiment, a method may include: etching asemiconductor substrate to form a semiconductor fin having a top surfaceand a sidewall with different crystal planes such that a thermal oxidelayer is grown to different thicknesses; thermally oxidizing thesemiconductor substrate to form a first thermal oxide layer on thesidewall of the semiconductor fin and form a second thermal oxide layeron the top surface of the semiconductor fin, wherein the second thermaloxide layers is thicker than the second thermal oxide layer; and forminga gate electrode on the first and second thermal oxide layers.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present inventionwill become more apparent to those of ordinary skill in the art bydescribing in detail exemplary embodiments thereof with reference to theattached drawings, in which:

FIG. 1 illustrates a perspective view for explaining the problem of atri-gate fin field effect transistor (FinFET);

FIG. 2 illustrates a perspective view of a dual-gate FinFET;

FIG. 3 illustrates a perspective view for explaining the problem of thedual-gate FinFET shown in FIG. 2;

FIGS. 4 through 6 illustrate perspective views for explaining theproblem of a method of manufacturing the dual-gate FinFET shown in FIG.2;

FIG. 7 illustrates equivalent crystal planes of a crystal plane {100}due to rotation of a lattice;

FIG. 8 illustrates the directions of lattices;

FIG. 9 illustrates crystal planes {100} and {110}, which are at rightangles to each other;

FIG. 10 illustrates a graph of the thicknesses of oxide layers formed oncrystal planes {100} and {110} under the same thermal oxidationconditions;

FIGS. 11 through 20 illustrate perspective views of stages of a methodof manufacturing a FinFET according to an exemplary embodiment of thepresent invention;

FIGS. 21 and 23 through 24 illustrates perspective views of stages of amethod of manufacturing a FinFET according to another exemplaryembodiment of the present invention;

FIG. 22 illustrates a stereogram of a substrate to be used in the methodof FIGS. 21 and 23 through 24.

DETAILED DESCRIPTION

Korean Patent Application 2006-124950, filed on Dec. 8, 2006, in theKorean Intellectual Property Office, and entitled: “FinFET and Method ofManufacturing the Same,” is incorporated by reference herein in itsentirety.

Embodiments will now be described more fully hereinafter with referenceto the accompanying drawings, in which example embodiments areillustrated. This invention, however, may be embodied in many differentforms and should not be construed as limited to the embodiments setforth herein. Rather, these embodiments are provided so that thisdisclosure will be thorough and complete, and will fully convey thescope of the invention to those skilled in the art. In the drawings, thethicknesses of layers and regions are exaggerated for clarity. It willalso be understood that when a layer is referred to as being on or underanother layer or substrate, it may be directly on or under the otherlayer or substrate, or intervening layers may also be present. Likenumbers refer to like elements throughout.

FIG. 1 illustrates a perspective view for explaining the problem of atri-gate fin field effect transistor (FinFET) 10.

Referring to FIG. 1, as the integration density of semiconductor devicesincreases, a width of a fin 20 of the tri-gate FinFET 10 decreases.After the fin 20 undergoes several processes, the shape of the fin 20may become pointed (indicated as portion “A”). As a result, a verticalgate field may crowd the fin 20, thus lowering electricalcharacteristics, such as a subthreshold swing, a threshold voltage, anda subthreshold current leakage. Also, while a gate conductive layer 30 ais being etched to form a gate electrode 30, the fin 20 that underliesthe gate conductive layer 30 a may be etched. Thus, a region wheresource and drain regions 30 a of the fin 20 will be formed may be at alower level than a region where a channel 20 a will be formed (indicatedas portion “B”).

In order to overcome the foregoing drawbacks, as illustrated in FIG. 2,a dual-gate FinFET 150 in which a capping layer 120 is formed on a fin110 has been developed. Specifically, the capping layer 120 may beformed on a top surface of the fin 110 to inhibit the generation of avertical gate field and keep an original shape of the fin 110. Also, thecapping layer 120 may protect the fin 110 during an etching process forforming a gate electrode 130, thereby preventing or reducing etching ofsource and drain regions 110 a.

However, even the capping layer 120 shown in FIG. 2 may be etched duringseveral processes for forming a channel region. As a result, the cappinglayer 120 may be completely removed or a damaged capping layer 120 b maybe left, as illustrated in FIG. 3. The damaged capping layer 120 a maynot properly perform its functions, so that similar problems as those ofthe tri-gate FinFET described with reference to FIG. 1 are likely tooccur.

The reason why the shape of the capping layer 120 may be damaged duringthe formation of the dual-gate FinFET 150 of FIG. 2 will now bedescribed with reference to FIGS. 4 through 6.

Referring to FIG. 4, a silicon nitride layer is formed on a siliconsubstrate. The silicon nitride layer may be formed using a chemicalvapor deposition (CVD) process. The silicon nitride layer may bepatterned to form the capping layer 120. Thereafter, the siliconsubstrate may be etched using the capping layer 120 as an etch mask,thereby forming the fin 110 that protrudes from an etched siliconsubstrate 100 a and extends in a first direction. In order to cure thedamage of sidewalls of the fin 110 caused by the etching of the siliconsubstrate, a sidewall oxide layer 112 may be formed on the sidewalls ofthe fin 110 using a thermal oxidation process. A silicon nitride layer114, which may serve as a liner, may be formed using a CVD technique tocover the sidewall oxide layer 112 and the capping layer 120 in order toprevent the oxidation of the sidewalls of the fin 110 during asubsequent process. Thereafter, a device isolation layer 116 may befilled from an upper surface of the silicon nitride layer 114 to a lowerportion 110 b of the fin 110, i.e., does not extend all the way upsidewalls of the fin 110.

Referring to FIG. 5, to form a channel region, a portion of the siliconnitride layer 114, which is exposed by the device isolation layer 116,is etched to form a silicon nitride layer pattern 114 a. The siliconnitride layer 114 may be etched using a phosphoric acid (H₃PO₄)solution. In this case, the capping layer 120, which may be the samelayer as the silicon nitride layer 114 serving as the liner, may also beetched by the H₃PO₄ solution. Although it is possible to reduce theetched amount of the capping layer 120 by optimizing etching conditionsusing the H₃PO₄ solution, etching of the capping layer 120 to someextent is practically inevitable, since the capping layer 120 is exposedto the H₃PO₄ solution. Therefore, a deformed capping layer 120 a may beformed as illustrated in FIG. 5 or the capping layer 120 may becompletely removed.

Subsequently, the sidewall oxide layer 112 exposed by the siliconnitride layer pattern 114 a may be etched to form a sidewall oxide layerpattern 112 a. In this case, the sidewall oxide layer 112 is etchedusing a fluoric acid (HF) solution. Thus, an upper portion 110 a of thefin 110 is exposed.

Referring to FIG. 6, a gate electrode 130 may be formed. The gateelectrode 13 may enclose the upper portion 110 a of the fin 110 exposedby the sidewall oxide layer pattern 112 and may extend in a seconddirection. In this case, the capping layer 120 a may be further etchedduring a process for forming the gate electrode 130, e.g., a dry etchingprocess. Thus, a further-etched capping layer 120 b may be formed.

As described above, since the capping layer 120 is exposed to severaletching processes, there is a strong likelihood that the capping layer120 may be greatly damaged or completely removed.

Embodiments of the present invention may provide a FinFET using asemiconductor fin. In an exemplary embodiment, the semiconductor fin mayinclude a top surface and a sidewall having different crystal planes.For example, when a silicon substrate is grown to have a plane {110}, anindex system for a crystal plane in an active layout for forming the finis set such that the sidewall of the fin has a plane {100}.

Hereinafter, crystallography will be briefly explained to facilitate anunderstanding of the embodiments of the present invention. In dealingwith crystal structures, it is very useful to refer to a lattice planeor a lattice direction. In a notation used for describing a plane or adirection, a set of three integers is adopted to indicate the positionof a plane or the direction of a vector in a lattice. Three integersused to describe a certain plane in a crystal lattice may be determinedas set forth below.

At the outset, intersections at which the certain plane meets threecrystal axes are found and expressed as integer-folds of a basic vector.In this case, the plane may move while leaving its orientation intact,until the intersections between the plane and the crystal axes arefound. The reciprocals of the intersections are taken, and a set ofthree integers h, k, and l, which has the smallest ratio of integers, isobtained while maintaining the same relationships. The three integers h,k, and l may be expressed using round brackets ().

The set of three integers h, k, and l is referred to as a Miller indexand used to define parallel planes in a lattice. From the standpoint ofcrystallography, many planes in a lattice are equivalent. In otherwords, a certain plane having a given Miller index may move in a latticeonly according to a method of selecting the position and orientation ofa unit cell. That is, planes, which are symmetric with respect to acrystal lattice axis, are called equivalent planes in thecrystallographic aspect. The crystallographically equivalent planes areexpressed using squiggled brackets { } instead of round brackets ().Thus, a crystal plane {100} includes three equivalent planes (100),(010), and (001). FIG. 7 illustrates the equivalent crystal planes(100), (010), and (001) of the crystal plane {100} due to rotation of alattice.

Meanwhile, a direction in a lattice is indicated as a set of threeintegers that have the same relationship as components of a vectorhaving the direction. Three components of the vector are expressed asproducts of a basic vector, converted into the smallest ratio ofintegers, and expressed using square brackets [ ]. Like the latticeplane, many directions in a lattice are equivalent, and equivalentdirections are expressed using angled brackets < >. For example, adirection <110> includes three crystallographically equivalentdirections [100], [010], and [001]. FIG. 8 illustrates the directions oflattices. From FIGS. 7 and 8, it can be seen that a direction [hkl] isvertical to a crystal plane (hkl).

Referring to FIG. 9, from the foregoing outline of crystallography, itcan be seen that, for a cubic crystal, a crystal plane (001) is at aright angle to a crystal plane (110), which corresponds to a direction[110]. In other words, it can be seen that a crystal plane {100} is at aright angle to a crystal plane {110}, which corresponds to a direction<110>. Thus, when a substrate having a crystal plane {110} is etched ina direction <110>, the etched section of the substrate has the crystalplane {110}. Also, when a substrate having a crystal plane {111} is cutin a direction <100>, the cut section of the substrate has a crystalplane {100}. When a substrate having a crystal plane {111} is cut in adirection <110>, the cut section of the substrate has a crystal plane{110}.

FIG. 10 illustrates a graph of thicknesses of oxide layers formed oncrystal planes {100} and {110} of a silicon crystal under the samethermal oxidation conditions. In FIG. 10, an abscissa denotes thethickness of a thermal oxide layer formed on the crystal plane {100},and an ordinate denotes the thickness of a thermal oxide layer formed onthe crystal plane {110}.

Based on the experimental results shown in FIG. 10, embodiments of thepresent invention may provide a semiconductor fin having differentcrystal planes. The different planes may have different atom densities,such that when a thermal oxidation process is performed under the sameprocess conditions, thermal oxide layers having different thicknessesmay be formed. In embodiments, a sidewall and a top surface of thesemiconductor fin may have different crystal planes with different atomdensities, so that a thermal oxide layer may be formed to differentthicknesses on the sidewall and top surface of the semiconductor fin.For example, the sidewall of the semiconductor fin may have a crystalplane {100}, while the top surface of the semiconductor fin may have acrystal plane {110}. Accordingly, the thermal oxide layer may be grownto a thicker thickness on the crystal plane {110} than on the crystalplane {100}. In other words, a thick thermal oxide layer may be grown onthe top surface having the crystal plane {110}, while a thin thermaloxide layer may be grown on the sidewall having the crystal plane {100}.Thus, a thick thermal oxide layer, which may replace the mask, may beformed without an additional process.

A substrate used for manufacturing a FinFET according to embodiments ofthe present invention may be a single crystalline bulk siliconsubstrate, which may be cut from a single crystalline silicon ingotformed using, for example, a Czochralski technique or a float zonegrowth technique, or a semiconductor substrate, which may include, e.g.,an epitaxial layer, a buried oxide layer, and a doping region to improvecharacteristics and obtain a desired structure. In addition, thesemiconductor substrate may be a silicon-on-insulator (SOI) substrateincluding a base substrate, a buried oxide layer, and a semiconductorsubstrate that are stacked sequentially.

FIGS. 11 through 20 illustrate perspective views of stages in a methodof manufacturing a FinFET according to an exemplary embodiment of thepresent invention. In the current embodiment, a substrate may be a bulksilicon substrate including a silicon layer grown to have a crystalplane {110} or a SOI substrate.

Referring to FIG. 11, a first oxide layer 202 may be formed on a siliconsubstrate 200. The first oxide layer 202 may be obtained by oxidizingthe surface of the silicon substrate 200 using, for example, a rapidthermal oxidation process, a furnace thermal oxidation process, or aplasma oxidation process. The first oxide layer 202 may be formed to athickness of about 10 to 100 Å.

Thereafter, a hard mask layer and a silicon nitride layer 204functioning as a capping layer may be formed on the first oxide layer202. The silicon nitride layer 204 may be obtained by depositing siliconnitride on the first oxide layer 202 using, for example, a low-pressureCVD (LPCVD) technique.

Referring to FIG. 12, photoresist (not shown) may be coated on thesilicon nitride layer 204 and patterned using a photolithography processto form a photoresist pattern (not shown). The silicon nitride layer 204and the first oxide layer 202 may be etched using the photoresistpattern as an etch mask, thereby forming an etch mask 206 including asilicon nitride layer pattern 204 a and a first oxide layer pattern 202a. Thereafter, the photoresist pattern may be removed, e.g., usingashing, stripping, and cleaning processes. Patterning the siliconnitride layer 204 and the first oxide layer 202 may be performed usingan active mask having a layout such that a sidewall of a fin has acrystal plane {100}, in order to induce a difference in oxide thicknesswith respect to a crystal plane during a subsequent process of forming agate thermal oxide layer. That is, a direction of the etch mask 206formed on the substrate 200 having the crystal plane {110} may bedetermined such that a lateral surface of the etched substratecorresponding to the sidewall of the fin has a crystal plane {100}.

Referring to FIG. 13, the exposed silicon substrate 200 may be dryetched using the silicon nitride layer pattern 204 a as an etch mask toform an active pattern 210. The active pattern 210 may protrude from thesurface of an etched silicon substrate 200 a and may extend across theetched silicon substrate 200 a. The active pattern 210 may have a heightof about 1500 to 4000 Å. The active pattern 210 may be referred to as a“fin.” An orientation of the semiconductor substrate 200 a may be setsuch that a top surface of the active pattern 210 has a plane (110) anda sidewall of the active pattern 210 has a plane (100).

Referring to FIG. 14, in order to reduce stress applied to the sidewallof the active pattern 210 during the etching of the semiconductorsubstrate 200, a second oxide layer 212 may be sequentially formed onthe surface of the silicon substrate 200 a and the surface of the activepattern 210. The second oxide layer 212 may be obtained by oxidizing,e.g., using a rapid thermal oxidation process, a furnace thermaloxidation process, or a plasma oxidation process, the surfaces of thesilicon substrate 200 a and the active pattern 210. The second oxidelayer 212 may be referred to as a “sidewall oxide layer.”

Referring to FIG. 15, after forming the active pattern 210, a dielectriclayer (or a field oxide layer) may be formed to bury the active pattern210 and then may be planarized. The dielectric layer may be formed,e.g., of a high-density plasma oxide or a spin-on-glass (SOG) material.The dielectric layer may be deposited to a thickness greater than theheight of the active pattern 210. The dielectric layer may be planarizedusing a chemical mechanical polishing (CMP) process or an etchbackprocess, thereby forming a dielectric layer pattern 220. Thereafter, theremaining etch mask 206, including the silicon nitride layer pattern 204a and the first oxide layer pattern 202 a, may be removed, e.g., usingan etching process, from the top surface of the active pattern 210.

Referring to FIG. 16, a hard mask 230 may be formed on top of the activepattern 210 and the dielectric layer pattern 220. The hard mask 230 maybe formed of a material having a high etch selectivity with respect tothe dielectric layer pattern 220, for example, silicon nitride (SiN),polysilicon (poly-Si), or silicon oxynitride (SiON), or of a materialhaving no etch selectivity with respect to the dielectric layer pattern220. The hard mask 230 may be formed to a thickness of, for example,about 500 to 2000 Å.

Referring to FIG. 17, in order to form a Damascene gate pattern, thehard mask 230 may be patterned using photolithographic and etchingprocesses, thereby forming a hard mask pattern 240.

Referring to FIG. 18, the dielectric layer pattern 220 may be recessedto a predetermined depth using the hard mask pattern 240. For example,the dielectric layer pattern 220 may be recessed to a depth of about 500to 1000 Å. When the hard mask pattern 240 is formed of a material havinga high etch selectivity with respect to the dielectric layer pattern220, for example, silicon nitride (SiN), polysilicon (poly-Si), orsilicon oxynitride (SiON), only a small amount of the hard mask pattern240 may be etched during the recessing of the dielectric layer pattern220 due to the high etch selectivity. However, when the hard maskpattern 240 is formed of a material having no etch selectivity withrespect to the dielectric layer pattern 220, the hard mask pattern 240may be etched as much as the dielectric layer pattern 220 during therecessing of the dielectric layer pattern 220. Accordingly, thethickness of the hard mask pattern 240 may be substantially equal to orgreater than the depth to which the dielectric pattern 220 is to berecessed.

Referring to FIG. 19, any remaining portion of the hard mask pattern 240may be removed, and gate dielectric layers 250 a and 250 b may beformed, e.g., using a thermal oxidation process, on the top and thesidewall, respectively, of the exposed active pattern 210. Since the topof the active pattern 210 has a crystal plane {110} and the sidewall ofthe active pattern 210 has a crystal plane {100}, the gate dielectriclayer 250 a formed on the top of the active pattern 210 is thicker thanthe gate dielectric layer 250 b formed on sidewalls of the activepattern 210. The thermal oxidation process may be, e.g., a wet oxidationprocess, a dry oxidation process, etc.

Referring to FIG. 20, a conductive material layer for a gate electrodemay be deposited on exposed portions of the gate dielectric layers 250 aand 250 b. The conductive material layer may be patterned usingphotolithographic and etching processes to form a gate electrode 260.

Since the hard mask pattern 240 has been removed before the gatedielectric layers 250 a and 250 b are formed, a gate dielectric layermay also be formed on source and drain regions. Therefore, when formingthe gate electrode 260, the gate dielectric layer formed on the sourceand drain regions may be removed, e.g., using an over-etching process.

The conductive material layer used for forming the gate electrode 260may be a single layer or a stacked layer, and may include, e.g., N-typeor P-type poly-Si, titanium nitride (TiN), tungsten (W), and tungstennitride (WN). To form the gate electrode 260, the conductive materiallayer may be formed to a thickness greater than the height of the activepattern 210. Specifically, the conductive material layer may be formedto a thickness of about 500 to 2000 Å. Since subsequent processes arethe same as processes for manufacturing an ordinary transistor, adescription thereof will not be presented here.

FIGS. 21 and 23 through 24 illustrate diagrams of stages in a method ofmanufacturing a FinFET according to another exemplary embodiment. In thecurrent embodiment, a substrate may be a bulk silicon substrate or a SOIsubstrate including a silicon layer grown to have a crystal plane {110}.

The current embodiment is a variation of the previous embodimentdescribed with reference to FIGS. 11 through 20. Thus, since theprocesses performed up until recessing a dielectric layer pattern 220using a hard mask pattern 240, as described with reference to FIGS. 11through 18, are the same as the processes of the previous embodiment,the description will begin with subsequent processes.

Referring to FIG. 21, the dielectric layer pattern 220 may be recessedusing the hard mask pattern 240 as described with reference to FIG. 18,and the active pattern 210 may also be recessed to a predetermined depthto form a recessed lateral surface 270. When the active pattern 210 isrecessed using a process incorporating a low etch selectivity betweensilicon and a dielectric layer, the dielectric layer pattern 220 may befurther recessed. In this case, when the active pattern 210 has arecessed depth of about 500 to 1500 Å, the firstly recessed depth andfurther recessed depth of the dielectric layer pattern 220 may sum up toabout 800 to 2500 Å. Thus, a step difference between the recessed activepattern 210 and the recessed dielectric layer pattern 220 may range fromabout 300 to 1000 Å.

Alternatively, when the active pattern 210 is recessed using a processincorporating a high etch selectivity between silicon and a dielectriclayer, the recessed depth of the active pattern 210 may be higher thanthe recessed depth of the dielectric layer pattern 220 in order toexpose the sidewall of the active pattern 210. In this case, therecessed depth of the active pattern 210 may be controlled such that astep difference between the recessed active pattern 210 and the recesseddielectric layer pattern 220 may range from about 300 to 1000 Å. In bothcases, the dielectric layer pattern 220 may be recessed to a greaterdepth than the active pattern 210.

As can be seen from the stereogram in FIG. 22, when a top of the activepattern 210 (i.e., the fin) has a crystal plane {110}, and a sidewall ofthe active pattern 210 has a crystal plane {100}, the recessed lateralsurface 270 may have a crystal plane {110}, which iscrystallographically vertical to the crystal plane {100} of the sidewallof the active pattern 210, In another implementation, the recessedlateral surface 270 may form an acute angle with the crystal plane {100}of the sidewall of the active pattern 210 according to recessingconditions. When the recessed lateral surface 270 forms an acute anglewith the sidewall of the active pattern 210, the recessed siliconlateral surface 270 may have one of crystal planes {111} and {113}between the crystal planes {100} and {110}. Since the crystal planes{111} and {113} are higher index planes than the crystal plane {100}, athick oxide layer may be formed on the recessed lateral surface 270during a subsequent thermal oxidation process.

Referring to FIG. 23, the hard mask pattern 240 may be removed, and gatedielectric layers 250 a and 250 b may be respectively formed on a topand sidewall of the exposed active pattern 210 using a thermal oxidationprocess. The thermal oxidation process may be, e.g., a wet oxidationprocess and a dry oxidation process. When the top of the active pattern210 has the crystal plane {110} and sidewalls of the active pattern 210have the crystal plane {100}, the thickness of oxide (Tox) is thicker onthe top of the active pattern 210 having the crystal plane {110} than onsidewalls of the active pattern 210 having the crystal plane {100}.Also, when the recessed silicon lateral surface 270 has the crystalplane {110} vertical to the crystal plane {100} of sidewalls of theactive pattern 210 or forms an acute angle with the crystal plane {100}of sidewalls of the active pattern 210 due to the crystallographicrelationship described with reference to FIG. 22, the thickness of oxide(Tox) is thicker on the recessed silicon lateral surface 270 having anycrystal plane than on the sidewalls of the active pattern 210 having thecrystal plane {100}.

Referring to FIG. 24, a gate electrode 260 may be formed in the samemanner as described with reference to FIG. 20. As described above, theembodiments of the present invention may provide a FinFET that maymaintain a reliable capping layer and an active interval. Generally, atleast one or more of these features may be realized by orienting a topsurface of the semiconductor fin on a first crystal plane (abc) and asidewall of the semiconductor fin on a second crystal plane (hkl),wherein a, b, and c are integers that are not all zero, h, k, and l areintegers that are not all zero, and a set of a, b, and c has at most twointegers in common with a set of h, k, and l.

In a FinFET according to embodiments of the present invention, anelectric field may be weakly applied from a gate electrode to the top ofa fin on which a thick thermal oxide layer is formed, while the electricfield may be strongly applied from the gate electrode to the sidewallsof the fin on which a thin thermal oxide layer is formed. Due to adifference between the electric fields applied to the top and sidewallsof the fin, the formation of a channel and a threshold voltage depend ona electric field applied to the sidewall of the fin. Therefore, a dropin the threshold voltage and the resultant degradation of the electricalcharacteristics of the FinFET may be effectively reduced or prevented,in contrast to a conventional FinFET in which the thickness of oxide(Tox) formed on the top of a fin is the same as that formed on thesidewall thereof.

Exemplary embodiments of the present invention have been disclosedherein, and although specific terms are employed, they are used and areto be interpreted in a generic and descriptive sense only and not forpurpose of limitation. Accordingly, it will be understood by those ofordinary skill in the art that various changes in form and details maybe made without departing from the spirit and scope of the presentinvention as set forth in the following claims.

1. A method of manufacturing a semiconductor device, comprising: forminga semiconductor fin having a top surface and a sidewall, the top surfacehaving a crystal plane {110} and the sidewall having a crystal plane{100}; forming a dielectric layer pattern extending along thesemiconductor fin; forming a gate dielectric layer including a firstportion on the sidewall of the semiconductor fin and a second portion onthe top surface of the semiconductor fin simultaneously, such that thesecond portion is thicker than the first portion; and forming a gateelectrode on the first and second portions, a lowermost surface of thegate electrode being lower than an uppermost surface of the dielectriclayer pattern; wherein: forming the first and second portions includes:forming a mask pattern on the dielectric layer pattern and the topsurface of the semiconductor fin to define a line region where a gateelectrode will be formed, the line region being substantiallyperpendicular to the semiconductor fin; partially etching the exposeddielectric layer pattern using the mask pattern as an etch mask toexpose the sidewall of the semiconductor fin; and thermally oxidizingthe top surface and sidewall of the semiconductor fin having thedifferent crystal planes.
 2. The method as claimed in claim 1, whereinforming the semiconductor fin comprises: preparing a semiconductorsubstrate having a crystal plane {110}; and etching the semiconductorsubstrate to create the sidewall of the semiconductor fin having acrystal plane {100}, wherein the dielectric layer pattern defines anactive region on the semiconductor substrate.
 3. The method as claimedin claim 1, wherein partially etching the exposed dielectric layerpattern using the mask pattern as the etch mask comprises partiallyetching the semiconductor fin to reduce a height of the semiconductorfin where the gate electrode is to be formed.
 4. A method ofmanufacturing a semiconductor device, comprising: etching asemiconductor substrate to form a semiconductor fin having a top surfaceand a sidewall, the top surface having a crystal plane {110} and thesidewall having a crystal plane {100}; forming a dielectric layerpattern extending along the semiconductor fin; thermally oxidizing thesemiconductor substrate to form a first thermal oxide layer on thesidewall of the semiconductor fin and to form a second thermal oxidelayer on the top surface of the semiconductor fin, such that the secondthermal oxide layer is thicker than the first thermal oxide layer; andforming a gate electrode on the first and second thermal oxide layers,wherein: the first thermal oxide layer and the second thermal oxidelayer are simultaneously formed; and forming the first and secondthermal oxide layers includes: forming a mask pattern on the dielectriclayer pattern and the top surface of the semiconductor fin to define aline region where a gate electrode will be formed, the line region beingsubstantially perpendicular to the semiconductor fin, partially etchingthe exposed dielectric layer pattern using the mask pattern as an etchmask to expose the sidewall of the semiconductor fin; and thermallyoxidizing the top surface and sidewall of the semiconductor fin havingthe different crystal planes.
 5. The method as claimed in claim 4,further comprising, before forming the gate electrode, reducing a heightof the semiconductor fin where the gate electrode is to be formed.
 6. Amethod of manufacturing a semiconductor device, comprising: etching asemiconductor substrate to form a semiconductor fin extending in a firstdirection and having a top surface and a sidewall, the top surfacehaving a crystal plane{110} and the sidewall having a crystal plane{100}; forming a dielectric layer pattern defining an active region ofthe substrate; planarizing the dielectric layer pattern to expose thetop surface of the semiconductor fin; forming a first mask patternextending in a second direction crossing the first direction to define aline region where a gate electrode will be formed, the line region beingsubstantially perpendicular to the semiconductor fin; removing a portionof the dielectric layer pattern according to the mask pattern to exposea portion of the sidewall of the semiconductor fin; thermally oxidizingthe top surface and sidewall of the semiconductor fin having thedifferent crystal planes to form a first thermal oxide layer on thesidewall of the semiconductor fin and a second thermal oxide layer onthe top surface of the semiconductor fin simultaneously, such that thesecond thermal oxide layer is thicker than the first thermal oxidelayer; and forming a gate electrode to fill the removing portion of thedielectric layer pattern, the gate electrode extending in the seconddirection.
 7. The method as claimed in claim 6, wherein etching thesemiconductor substrate comprises forming a second mask pattern on thesemiconductor substrate.
 8. The method as claimed in claim 7, whereinplanarizing the dielectric layer pattern comprises removing the secondmask pattern to expose the top surface of the semiconductor fin.
 9. Themethod as claimed in claim 6, wherein an uppermost surface of thedielectric layer pattern is coplanar with the top surface of thesemiconductor fin.
 10. The method as claimed in claim 6, wherein alowermost surface of the gate electrode is lower than an uppermostsurface of the dielectric layer pattern.
 11. The method as claimed inclaim 6, further comprising forming a second oxide layer between thesemiconductor fin and the dielectric layer pattern.
 12. The method asclaimed in claim 6, further comprising recessing the exposed portion ofthe semiconductor fin to reduce a height of the semiconductor fin beforethermally oxidizing the semiconductor substrate.
 13. The method asclaimed in claim 12, wherein recessing the exposed portion of thesemiconductor fin comprises recessing the dielectric layer pattern usinga low etch selectivity etchant.